
Chapter 1: ML405 Evaluation Platform
3 . Differential Clock Input and Output with SMA Connectors
High-precision clock signals can be input to the FPGA using differential clock signals
brought in through 50 Ω SMA connectors. This allows an external function generator or
other clock source to drive the differential clock inputs that directly feed the global clock
input pins of the FPGA. The FPGA can be configured to present a 100 Ω termination
impedance.
A differential clock output from the FPGA is driven out through a second pair of SMA
connectors. This allows the FPGA to drive a precision clock to an external device, such as
a piece of test equipment. Table 1-3 summarizes the differential SMA clock pin
connections.
R
Table 1-3:
Differential SMA Clock Connections
Label
J10
J7
J8
J9
Clock Name
SMA_DIFF_CLK_IN_N
SMA_DIFF_CLK_IN_P
SMA_DIFF_CLK_OUT_N
SMA_DIFF_CLK_OUT_P
FPGA Pin
B12
A12
H6
G7
4. Oscillator Sockets
The ML405 evaluation platform has two crystal oscillator sockets, each wired for standard
LVTTL-type oscillators. (A 100-MHz oscillator is pre-installed in the X1 SYSCLK socket.)
These connect to the FPGA clock pins as shown in Table 1-4 . The oscillator sockets accept
half-sized oscillators and are powered by the 3.3V supply.
Table 1-4:
Oscillator Socket Connections
Label
X1
X6
Clock Name
SYSCLK
USERCLK
FPGA Pin
AB14
AB12
5. LCD Brightness and Contrast Adjustment
Turning potentiometer R1 adjusts the image contrast of the character LCD.
6. DIP Switches (Not Installed)
These DIP switches are not installed on the ML405 board.
14
ML405 Evaluation Platform
UG210 (v1.5.1) March 10, 2008